Network-on-chip : : the next generation of system-on-chip integration / / Santanu Kundu, Santanu Chattopadhyay.
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with...
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Place / Publishing House: | Boca Raton, FL : : Taylor & Francis,, 2014. |
Year of Publication: | 2014 |
Language: | English |
Physical Description: | 1 online resource (xvii, 369 pages) :; illustrations |
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Kundu, Santanu, author. Network-on-chip : the next generation of system-on-chip integration / Santanu Kundu, Santanu Chattopadhyay. Network-on-Chip Boca Raton, FL : Taylor & Francis, 2014. 1 online resource (xvii, 369 pages) : illustrations text txt rdacontent computer c rdamedia online resource cr rdacarrier Description based on print version of record. Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC-its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems. Includes bibliographical references and index. 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends. Networks on a chip. Chattopadhyay, Santanu, author. |
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English |
format |
eBook |
author |
Kundu, Santanu, Chattopadhyay, Santanu, |
spellingShingle |
Kundu, Santanu, Chattopadhyay, Santanu, Network-on-chip : the next generation of system-on-chip integration / 1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends. |
author_facet |
Kundu, Santanu, Chattopadhyay, Santanu, Chattopadhyay, Santanu, |
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VerfasserIn VerfasserIn |
author2 |
Chattopadhyay, Santanu, |
author2_role |
TeilnehmendeR |
author_sort |
Kundu, Santanu, |
title |
Network-on-chip : the next generation of system-on-chip integration / |
title_sub |
the next generation of system-on-chip integration / |
title_full |
Network-on-chip : the next generation of system-on-chip integration / Santanu Kundu, Santanu Chattopadhyay. |
title_fullStr |
Network-on-chip : the next generation of system-on-chip integration / Santanu Kundu, Santanu Chattopadhyay. |
title_full_unstemmed |
Network-on-chip : the next generation of system-on-chip integration / Santanu Kundu, Santanu Chattopadhyay. |
title_auth |
Network-on-chip : the next generation of system-on-chip integration / |
title_alt |
Network-on-Chip |
title_new |
Network-on-chip : |
title_sort |
network-on-chip : the next generation of system-on-chip integration / |
publisher |
Taylor & Francis, |
publishDate |
2014 |
physical |
1 online resource (xvii, 369 pages) : illustrations |
contents |
1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends. |
callnumber-first |
T - Technology |
callnumber-subject |
TK - Electrical and Nuclear Engineering |
callnumber-label |
TK5105 |
callnumber-sort |
TK 45105.546 K863 42014 |
illustrated |
Illustrated |
dewey-hundreds |
600 - Technology |
dewey-tens |
620 - Engineering |
dewey-ones |
621 - Applied physics |
dewey-full |
621.381531 |
dewey-sort |
3621.381531 |
dewey-raw |
621.381531 |
dewey-search |
621.381531 |
work_keys_str_mv |
AT kundusantanu networkonchipthenextgenerationofsystemonchipintegration AT chattopadhyaysantanu networkonchipthenextgenerationofsystemonchipintegration AT kundusantanu networkonchip AT chattopadhyaysantanu networkonchip |
status_str |
n |
ids_txt_mv |
(CKB)5470000000568701 (NjHacI)995470000000568701 (EXLCZ)995470000000568701 |
carrierType_str_mv |
cr |
is_hierarchy_title |
Network-on-chip : the next generation of system-on-chip integration / |
author2_original_writing_str_mv |
noLinkedField |
_version_ |
1796651466971152384 |
fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04074nam a2200301 i 4500</leader><controlfield tag="001">993545011904498</controlfield><controlfield tag="005">20230329135343.0</controlfield><controlfield tag="006">m o d </controlfield><controlfield tag="007">cr |||||||||||</controlfield><controlfield tag="008">230329s2014 flua ob 001 0 eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(CKB)5470000000568701</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(NjHacI)995470000000568701</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(EXLCZ)995470000000568701</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">NjHacI</subfield><subfield code="b">eng</subfield><subfield code="e">rda</subfield><subfield code="c">NjHacl</subfield></datafield><datafield tag="050" ind1=" " ind2="4"><subfield code="a">TK5105.546</subfield><subfield code="b">.K863 2014</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">621.381531</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kundu, Santanu,</subfield><subfield code="e">author.</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Network-on-chip :</subfield><subfield code="b">the next generation of system-on-chip integration /</subfield><subfield code="c">Santanu Kundu, Santanu Chattopadhyay.</subfield></datafield><datafield tag="246" ind1=" " ind2=" "><subfield code="a">Network-on-Chip </subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boca Raton, FL :</subfield><subfield code="b">Taylor & Francis,</subfield><subfield code="c">2014.</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xvii, 369 pages) :</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">computer</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">online resource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="588" ind1=" " ind2=" "><subfield code="a">Description based on print version of record.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC-its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.</subfield></datafield><datafield tag="504" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index.</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends.</subfield></datafield><datafield tag="650" ind1=" " ind2="0"><subfield code="a">Networks on a chip.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Chattopadhyay, Santanu,</subfield><subfield code="e">author.</subfield></datafield><datafield tag="906" ind1=" " ind2=" "><subfield code="a">BOOK</subfield></datafield><datafield tag="ADM" ind1=" " ind2=" "><subfield code="b">2023-04-15 12:12:50 Europe/Vienna</subfield><subfield code="f">system</subfield><subfield code="c">marc21</subfield><subfield code="a">2021-06-12 22:12:12 Europe/Vienna</subfield><subfield code="g">false</subfield></datafield><datafield tag="AVE" ind1=" " ind2=" "><subfield code="i">DOAB Directory of Open Access Books</subfield><subfield code="P">DOAB Directory of Open Access Books</subfield><subfield code="x">https://eu02.alma.exlibrisgroup.com/view/uresolver/43ACC_OEAW/openurl?u.ignore_date_coverage=true&portfolio_pid=5337766130004498&Force_direct=true</subfield><subfield code="Z">5337766130004498</subfield><subfield code="b">Available</subfield><subfield code="8">5337766130004498</subfield></datafield></record></collection> |