Compact Models for Integrated Circuit Design : : Conventional Transistors and Beyond.

Compact Models for Integrated Circuit Design : : Conventional Transistors and Beyond.

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Bibliographic Details
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Saha, Samar K.
Place / Publishing House:Milton : : Taylor & Francis Group,, 2015.
Ã2016.
Year of Publication:2015
Edition:1st ed.
Language:English
Online Access:
Physical Description:1 online resource (548 pages)
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Table of Contents:
  • Cover
  • Half Title
  • Title Page
  • Copyright Page
  • Dedication
  • Table of Contents
  • Preface
  • Author
  • 1: Introduction to Compact Models
  • 1.1 Compact Models for Circuit Simulation
  • 1.1.1 Compact Device Models
  • 1.1.2 Compact Interconnect Models
  • 1.2 Brief History of Compact Device Modeling
  • 1.2.1 Early History of Compact MOSFET Modeling
  • 1.2.2 Recent History of Compact MOSFET Modeling
  • 1.2.2.1 Threshold Voltage-Based Compact MOSFET Modeling
  • 1.2.2.2 Surface Potential-Based Compact MOSFET Modeling
  • 1.2.2.3 Charge-Based Compact MOSFET Modeling
  • 1.3 Motivation for Compact Modeling
  • 1.4 Compact Model Usage
  • 1.5 Compact Model Standardization
  • 1.6 Summary
  • Exercises
  • 2: Review of Basic Device Physics
  • 2.1 Introduction
  • 2.2 Semiconductor Physics
  • 2.2.1 Energy Band Model
  • 2.2.2 Carrier Statistics
  • 2.2.3 Intrinsic Semiconductors
  • 2.2.3.1 Intrinsic Carrier Concentration
  • 2.2.3.2 Effective Mass of Electrons and Holes
  • 2.2.4 Extrinsic Semiconductors
  • 2.2.4.1 Fermi Level in Extrinsic Semiconductor
  • 2.2.4.2 Fermi Level in Degenerately Doped Semiconductor
  • 2.2.5 Carrier Transport in Semiconductors
  • 2.2.5.1 Carrier Mobility and Drift Current
  • 2.2.5.2 Electrical Resistivity
  • 2.2.5.3 Sheet Resistance
  • 2.2.5.4 Velocity Saturation
  • 2.2.5.5 Diffusion of Carriers
  • 2.2.5.6 Nonuniformly Doped Semiconductors and Built-In Electric Field
  • 2.2.6 Generation-Recombination
  • 2.2.6.1 Injection Level
  • 2.2.6.2 Recombination Processes
  • 2.2.7 Basic Semiconductor Equations
  • 2.2.7.1 Poisson's Equation
  • 2.2.7.2 Carrier Concentration in Terms of Electrostatic Potential
  • 2.2.7.3 Quasi-Fermi Level
  • 2.2.7.4 Transport Equations
  • 2.2.7.5 Continuity Equations
  • 2.3 Theory of n-Type and p-Type Semiconductors in Contact
  • 2.3.1 Basic Features of pn-Junctions
  • 2.3.2 Built-In Potential.
  • 2.3.3 Step Junctions
  • 2.3.3.1 Junction Potential and Electric Field
  • 2.3.4 pn-Junctions under External Bias
  • 2.3.4.1 One-Sided Step Junctions
  • 2.3.5 pn-Junction Equations
  • 2.3.5.1 Relationship between Minority Carrier Density and Junction Voltage
  • 2.3.6 pn-Junctions I-V Characteristics
  • 2.3.6.1 Temperature Dependence of pn-Junction Leakage Current
  • 2.3.6.2 Limitations of pn-Junction Current Equation
  • 2.3.6.3 Bulk Resistance
  • 2.3.6.4 Junction Breakdown Voltage
  • 2.3.7 pn-Junction Dynamic Behavior
  • 2.3.7.1 Junction Capacitance
  • 2.3.7.2 Diffusion Capacitance
  • 2.3.7.3 Small Signal Conductance
  • 2.3.8 Diode Equivalent Circuit for Circuit CAD
  • 2.4 Summary
  • Exercises
  • 3: Metal-Oxide-Semiconductor System
  • 3.1 Introduction
  • 3.2 MOS Capacitor at Equilibrium
  • 3.2.1 Work Function
  • 3.2.2 Oxide Charges
  • 3.2.2.1 Interface-Trapped Charge
  • 3.2.2.2 Fixed-Oxide Charge
  • 3.2.2.3 Oxide-Trapped Charge
  • 3.2.2.4 Mobile Ionic Charge
  • 3.2.3 Flat Band Voltage
  • 3.2.4 Effect of Band Bending on the Semiconductor Surface
  • 3.3 MOS Capacitor under Applied Bias
  • 3.3.1 Accumulation
  • 3.3.2 Depletion
  • 3.3.3 Inversion
  • 3.4 MOS Capacitor Theory
  • 3.4.1 Formulation of Poisson's Equation in Terms of Band-Bending Potential
  • 3.4.2 Electrostatic Potentials and Charge Distribution
  • 3.4.2.1 MOS Capacitor at Depletion: Depletion Approximation
  • 3.4.2.2 MOS Capacitor at Inversion
  • 3.5 Capacitance of MOS Structure
  • 3.5.1 Low Frequency C-V Characteristics
  • 3.5.1.1 Accumulation
  • 3.5.1.2 Flat Band
  • 3.5.1.3 Depletion
  • 3.5.1.4 Inversion
  • 3.5.2 Intermediate and High Frequency C-V Characteristics
  • 3.5.3 Deep Depletion C-V Characteristics
  • 3.5.4 Deviation from Ideal C-V Curves
  • 3.5.5 Polysilicon Depletion Effect on C-V Curves
  • 3.6 Summary
  • Exercises
  • 4: Large Geometry MOSFET Compact Models
  • 4.1 Introduction.
  • 4.2 Overview of MOSFET Devices
  • 4.2.1 Basic Features of MOSFET Devices
  • 4.2.2 MOSFET Device Operation
  • 4.3 MOSFET Threshold Voltage Model
  • 4.4 MOSFET Drain Current Model
  • 4.4.1 Drain Current Formulation
  • 4.4.2 Pao-Sah Model
  • 4.4.3 Charge-Sheet Model
  • 4.4.3.1 Drift Component of Drain Current
  • 4.4.3.2 Diffusion Component of Drain Current
  • 4.4.4 Regional Drain Current Model
  • 4.4.4.1 Core Model
  • 4.4.4.2 Bulk-Charge Model
  • 4.4.4.3 Square Root Approximation of Bulk-Charge Model
  • 4.4.4.4 Subthreshold Region Drain Current Model
  • 4.4.4.5 Limitations of Regional Drain Current Model
  • 4.5 Summary
  • Exercises
  • 5: Compact Models for Small Geometry MOSFETs
  • 5.1 Introduction
  • 5.2 Threshold Voltage Model
  • 5.2.1 Effect of Nonuniform Channel Doping on Threshold Voltage
  • 5.2.1.1 Threshold Voltage Modeling for Nonuniform Vertical Channel Doping Profile
  • 5.2.1.2 Threshold Voltage Modeling for Nonuniform Lateral Channel Doping Profile
  • 5.2.2 Small Geometry Effect on Threshold Voltage Model
  • 5.2.2.1 Threshold Voltage Model for Short Channel MOSFET Devices
  • 5.2.2.2 Threshold Voltage Modeling for Narrow Channel MOSFET Devices
  • 5.3 Drain Current Model
  • 5.3.1 Surface Mobility Model
  • 5.3.2 Subthreshold Region Drain Current Model
  • 5.3.3 Linear Region Drain Current Model
  • 5.3.4 Saturation Region Drain Current Model
  • 5.3.5 Bulk-Charge Effect
  • 5.3.6 Output Resistance
  • 5.3.7 Unified Drain Current Equation
  • 5.3.8 S/D Parasitic Series Resistance
  • 5.3.9 Polysilicon Gate Depletion
  • 5.3.10 Temperature Dependence
  • 5.4 Substrate Current Model
  • 5.4.1 Gate-Induced Drain Leakage Body Current Model
  • 5.4.2 Gate Current Model
  • 5.5 Summary
  • Exercises
  • 6: MOSFET Capacitance Models
  • 6.1 Introduction
  • 6.2 Basic MOSFET Capacitance Model
  • 6.2.1 Intrinsic Charges and Capacitances
  • 6.2.2 Meyer Model.
  • 6.2.2.1 Strong Inversion
  • 6.2.2.2 Weak Inversion
  • 6.2.3 Limitations of Meyer Model
  • 6.3 Charge-Based Capacitance Model
  • 6.3.1 Long Channel Charge Model
  • 6.3.1.1 Strong Inversion
  • 6.3.1.2 Weak Inversion
  • 6.3.1.3 Accumulation
  • 6.3.2 Long Channel Capacitance Model
  • 6.3.3 Short Channel Charge Model
  • 6.3.4 Short Channel Capacitance Model
  • 6.4 Gate Overlap Capacitance Model
  • 6.5 Limitations of the Quasistatic Model
  • 6.6 S/D pn-Junction Capacitance Model
  • 6.6.1 Source-Body pn-Junction Diode
  • 6.6.2 Drain-Body Junction Diode
  • 6.7 Summary
  • Exercises
  • 7: Compact MOSFET Models for RF Applications
  • 7.1 Introduction
  • 7.2 MOSFET Noise Models
  • 7.2.1 Fundamental Sources of Noise
  • 7.2.2 Thermal Noise
  • 7.2.2.1 Physical Mechanism of Thermal Noise
  • 7.2.2.2 Thermal Noise Model
  • 7.2.3 Flicker Noise
  • 7.2.3.1 Physical Mechanism of Flicker Noise
  • 7.2.3.2 Flicker Noise Model
  • 7.3 NQS Effect
  • 7.3.1 Modeling NQS Effect in MOSFETs
  • 7.4 Modeling Parasitic Elements for RF Applications
  • 7.4.1 Modeling Gate Resistance
  • 7.4.2 Modeling Substrate Network
  • 7.4.3 MOSFET RF Model for GHz Applications
  • 7.5 Summary
  • Exercises
  • 8: Modeling Process Variability in Scaled MOSFETs
  • 8.1 Introduction
  • 8.2 Sources of Front-End Process Variability
  • 8.2.1 Systematic or Global Process Variability
  • 8.2.2 Random or Local Process Variability
  • 8.2.2.1 Random Discrete Doping
  • 8.2.2.2 Line-Edge Roughness
  • 8.2.2.3 Oxide Thickness Variation
  • 8.2.2.4 Other Sources Process Variability
  • 8.3 Characterization of Parametric Variability in MOSFETs
  • 8.3.1 Random Variability
  • 8.3.2 Systematic Variability
  • 8.4 Conventional Process Variability Modeling for Circuit CAD
  • 8.4.1 Worst-Case Fixed Corner Models
  • 8.4.2 Statistical Corner Models
  • 8.4.3 Process Parameters-Based Compact Variability Modeling.
  • 8.5 Statistical Compact Modeling
  • 8.5.1 Determination of Process Variability-Sensitive MOSFET Device Parameters
  • 8.5.1.1 Selection of Local Process Variability-Sensitive Device Parameters
  • 8.5.1.2 Selection of Global Process Variability-Sensitive Device Parameters
  • 8.5.2 Mapping Process Variability-Sensitive Device Parameters to Compact Model Parameters
  • 8.5.2.1 Mapping Local Process Variability-Sensitive Device Parameters to Compact Model Parameters
  • 8.5.2.2 Mapping Global Process Variability-Sensitive Device Parameters to Compact Model Parameters
  • 8.5.3 Determination of Variance for Process Variability-Sensitive Compact Model Parameters
  • 8.5.3.1 Variance of Local Process Variability-Sensitive Compact Model Parameters
  • 8.5.3.2 Variance of the Global Process Variability-Sensitive Compact Model Parameters
  • 8.5.4 Formulation of Compact Model for Process Variability-Aware Circuit Design
  • 8.5.5 Simulation Results and Discussions
  • 8.6 Mitigation of the Risk of Process Variability in VLSI Circuit Performance
  • 8.7 Summary
  • Exercises
  • 9: Compact Models for Ultrathin Body FETs
  • 9.1 Introduction
  • 9.2 Multigate Device Structures
  • 9.2.1 Bulk-Multigate Device Structure
  • 9.2.2 UTB-SOI Device Structure
  • 9.3 Common Multiple-Gate FinFET Model
  • 9.3.1 Core Model: Poisson-Carrier Transport
  • 9.3.1.1 Electrostatics
  • 9.3.1.2 Drain Current Model
  • 9.3.2 Modeling Physical Effects of Real Device
  • 9.3.2.1 Short Channel Effects
  • 9.3.2.2 Quantum Mechanical Effects
  • 9.3.2.3 Mobility Degradation
  • 9.3.2.4 Series Resistances
  • 9.4 Independent Multiple-Gate FET Model
  • 9.4.1 Electrostatics
  • 9.4.2 Drain Current Model
  • 9.5 Dynamic Model
  • 9.5.1 Common Multigate C-V Model
  • 9.5.2 Independent Multigate C-V Model
  • 9.6 Summary
  • Exercises
  • 10: Beyond-CMOS Transistor Models: Tunnel FETs
  • 10.1 Introduction.
  • 10.2 Basic Features of TFETs.

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