A Journey of Embedded and Cyber-Physical Systems : : Essays Dedicated to Peter Marwedel on the Occasion of His 70th Birthday.

• Author: Chen, Jian-Jia.
• Place / Publishing House: Cham : : Springer International Publishing AG,, 2020.; Ã2021.
• Year of Publication: 2020
• Edition: 1st ed.
• Language: English
• Physical Description: 1 online resource (181 pages)

Table of Contents

• Intro
• Foreword
• Acknowledgements
• Contents
• Contributors
• 1 Peter Marwedel and the Department of Computer Science of the TU Dortmund University
• 1.1 Introduction
• 1.2 Teaching
• 1.3 Academic Self-Government
• 1.4 Basic Research and SFB 876
• 1.5 Technology Transfer and ICD
• 1.6 Conclusion
• 2 Testing Implementation Soundness of a WCET Analysis Tool
• 2.1 Introduction
• 2.1.1 Tool Qualification
• 2.1.2 Predictability
• 2.1.3 WCET Analysis
• 2.1.4 The Central Idea: Proving Safety Properties
• 2.1.5 Terminology
• 2.2 Validation of Our WCET Analysis Tool
• 2.2.1 Control-Flow Graph Reconstruction
• 2.2.2 Value Analysis
• 2.2.3 Microarchitectural Analysis: Trace Validation
• 2.2.3.1 Semi-Automatic Derivation of the Abstract Architecture Model
• 2.2.3.2 Trace Validation
• 2.3 Conclusion
• References
• 3 The Dynamic Random Access Memory Challenge in Embedded Computing Systems
• 3.1 Introduction
• 3.2 Bandwidth and Latency
• 3.3 Power Consumption
• 3.4 Temperature vs. Reliability
• 3.5 Safety and Security
• 3.6 Conclusion
• References
• 4 On the Formalism and Properties of Timing Analyses in Real-Time Embedded Systems
• 4.1 Introduction
• 4.2 Formal Analysis Based on Schedule Functions
• 4.2.1 Preemptive EDF
• 4.2.2 Preemptive Fixed-Priority Scheduling Algorithms
• 4.3 Utilization-Based Analyses for Fixed-Priority Scheduling
• 4.4 Probabilistic Schedulability Tests
• 4.5 Conclusion
• References
• 5 ASSISTECH: An Accidental Journey into Assistive Technology
• 5.1 The Beginning: Mainly a Facilitator (2000-2005)
• 5.2 Early Phase: Focus on Embedded Systems (2005-2010)
• 5.2.1 ASSISTECH and COP315
• 5.2.2 SmartCane
• 5.2.3 OnBoard
• 5.3 Collaborations and Research: Formation of ASSISTECH (2010-2013)
• 5.3.1 Student Projects to Research
• 5.3.2 NVDA Activities
• 5.3.3 TacRead and DotBook.
• 5.4 Change of Focus: Technology to Users (2013-2016)
• 5.4.1 Tactile Graphics Project
• 5.4.2 More Research Projects and International Collaboration
• 5.5 Consolidation and Growth (2016 - )
• 5.5.1 RAVI
• 5.5.2 MAVI
• 5.5.3 NAVI
• 5.5.4 Outreach Through Conferences
• 5.5.5 Major Recognitions
• 5.6 Conclusion
• References
• 6 Reflecting on Self-Aware Systems-on-Chip
• 6.1 Introduction to Self-Aware Systems-on-Chip
• 6.1.1 Computational Self-Awareness
• 6.1.2 Cyber-Physical Systems-on-Chip
• 6.2 Reflective System Models
• 6.2.1 Middleware for Reflective Decision-Making
• 6.3 Managing Energy-Efficient Chip Multiprocessors
• 6.3.1 Single Input Single Output Controllers
• 6.3.2 Multiple Input Multiple Output Controllers
• 6.3.3 Adaptive Control Methods
• 6.3.4 Hierarchical Controllers
• 6.4 Heterogeneous Mobile Governors: Energy-Efficient Mobile System-on-a-Chip
• 6.4.1 Sensors to Capture Dynamism
• 6.4.2 Toward Self-Aware Governors
• 6.5 Adaptive Memory: Managing Runtime Variability
• 6.5.1 Sharing Distributed Memory Space
• 6.5.2 Memory Phase Awareness
• 6.5.3 Quality-Configurable Memory
• 6.6 What's Ahead?
• 6.6.1 Example Use Case: Autonomous Driving
• 6.7 Summary
• References
• 7 Pushing the Limits of Parallel Discrete Event Simulation for SystemC
• 7.1 Introduction
• 7.2 RISC Framework
• 7.2.1 RISC Compiler
• 7.2.1.1 Segment Graph Construction
• 7.2.1.2 Conflict Analysis
• 7.2.1.3 Source Code Instrumentation
• 7.2.2 RISC Simulator
• 7.2.3 RISC Analysis and Transformation Tools
• 7.3 Experiments
• 7.3.1 Mandelbrot Renderer
• 7.4 RISC Open Source Project
• 7.4.1 Open Source Code and Documentation
• 7.4.2 Binary Image for ``Plug-and-Play'' Evaluation
• 7.5 Conclusion
• References
• 8 Impact of Negative Capacitance Field-Effect Transistor (NCFET) on Many-Core Systems
• 8.1 Introduction.
• 8.1.1 Negative Capacitance Field-Effect Transistor (NCFET)
• 8.2 Modeling NCFET at the System Level
• 8.2.1 Processor-Level Investigation
• 8.2.2 Simulation of NCFET-Based Many-Core
• 8.3 Performance, Power, and Cooling Trade-Offs with NCFET-based Many-Cores
• 8.3.1 Impact of NCFET on Performance
• 8.3.2 Impact of NCFET on Cooling Requirements
• 8.3.3 Impact of NCFET on Power Management Techniques
• 8.4 NCFET-Aware Voltage Scaling
• 8.4.1 Importance of NCFET-Aware DVS
• 8.4.2 NCFET-Aware DVS Technique
• 8.4.2.1 Design-Time Models
• 8.4.2.2 Runtime Models
• 8.4.3 Operating Voltage Selection
• 8.4.4 Evaluation
• 8.4.4.1 Experimental Setup
• 8.4.4.2 NCFET-Aware DVS Results and Analysis
• 8.5 Conclusion
• References
• 9 Run-Time Enforcement of Non-functional Program Properties on MPSoCs
• 9.1 Introduction
• 9.2 Preliminaries and Definitions
• 9.2.1 System Model
• 9.2.2 *-Predictability
• 9.3 Run-Time Requirement Enforcement
• 9.4 Taxonomy of Run-Time Requirement Enforcers
• 9.4.1 Enforcement Automata (EA)
• 9.4.2 i-lets and e-lets
• 9.5 Case Study
• 9.5.1 Enforcement Problem Description
• 9.5.2 Power, Latency, and Energy Model
• 9.5.3 Energy-Minimized Timing Enforcement
• 9.5.4 Distributed Enforcement
• 9.5.5 Centralized Enforcement
• 9.5.6 Lower Latency Bound Enforcement and Range Extenders
• 9.6 Conclusions
• References
• 10 Compilation for Real-Time Systems a Decade After Predator
• 10.1 Introduction
• 10.2 Challenges and State-of-the-Art in WCET-Aware Compilation During Predator
• 10.3 Integration of Task Coordination into WCET-Aware Compilation
• 10.4 Analysis and Optimization of Multi-Processor Systems on Chip
• 10.5 Multi-Objective Compiler Optimizations Under Real-Time Constraints
• 10.6 Conclusions
• References
• Index.