High-performance and time-predictable embedded computing / / editors, Luis Miguel Pinho [and six others].

• Superior document: River Publishers series in information science and technology
• TeilnehmendeR: Pinho, Luis Miguel,
• Place / Publishing House: Gistrup, Denmark : : River Publishers,, 2018.; ©2018
• Year of Publication: 2018
• Edition: 1st ed.
• Language: English
• Series: River Publishers series in information science and technology.
• Physical Description: 1 online resource (236 pages).

Journal of Cyber Security and Mobility provides an in-depth and holistic view of security and solutions from practical to theoretical aspects. It covers topics that are equally valuable for practitioners as well as those new in the field.

Table of Contents

Front Cover -- Half Title page -- RIVER PUBLISHERS SERIES IN INFORMATIONSCIENCE AND TECHNOLOGY -- Title page -- Copyright page -- Contents -- Preface -- List of Contributors -- List of Figures -- List of Tables -- List of Abbreviations -- Chapter 1 - Introduction -- 1.1 Introduction -- 1.1.1 The Convergence of High-performance and Embedded Computing Domains -- 1.1.2 Parallelization Challenge -- 1.2 The P-SOCRATES Project -- 1.3 Challenges Addressed in This Book -- 1.3.1 Compiler Analysis of Parallel Programs -- 1.3.2 Predictable Scheduling of Parallel Tasks on Many-core Systems -- 1.3.3 Methodology for Measurement-based Timing Analysis -- 1.3.4 Optimized OpenMP Tasking Runtime System -- 1.3.5 Real-time Operating Systems -- 1.4 The UpScale SDK -- 1.5 Summary -- References -- Chapter 2 - Manycore Platforms -- 2.1 Introduction -- 2.2 Manycore Architectures -- 2.2.1 Xeon Phi -- 2.2.2 Pezy SC -- 2.2.3 NVIDIA Tegra X1 -- 2.2.4 Tilera Tile -- 2.2.5 STMicroelectronics STHORM -- 2.2.6 Epiphany-V -- 2.2.7 TI Keystone II -- 2.2.8 Kalray MPPA-256 -- 2.2.8.1 The I/O subsystem -- 2.2.8.2 The Network-on-Chip (NoC) -- 2.2.8.3 The Host-to-IOS communication protocol -- 2.2.8.4 Internal architecture of the compute clusters -- 2.2.8.5 The shared memory -- 2.3 Summary -- References -- Chapter 3 - Predictable Parallel Programming with OpenMP -- 3.1 Introduction -- 3.1.1 Introduction to Parallel Programming Models -- 3.1.1.1 POSIX threads -- 3.1.1.2 OpenCLTM -- 3.1.1.3 NVIDIA R CUDA -- 3.1.1.4 Intel R CilkTM Plus -- 3.1.1.5 Intel R TBB -- 3.1.1.6 OpenMP -- 3.2 The OpenMP Parallel Programming Model -- 3.2.1 Introduction and Evolution of OpenMP -- 3.2.2 Parallel Model of OpenMP -- 3.2.2.1 Execution model -- 3.2.2.2 Acceleration model -- 3.2.2.3 Memory model -- 3.2.3 An OpenMP Example -- 3.3 Timing Properties of the OpenMP Tasking Model.

3.3.1 Sporadic DAG Scheduling Model of Parallel Applications -- 3.3.2 Understanding the OpenMP Tasking Model -- 3.3.3 OpenMP and Timing Predictability -- 3.3.3.1 Extracting the DAG of an OpenMP program -- 3.3.3.2 WCET analysis is applied to tasks and task parts -- 3.3.3.3 DAG-based scheduling must not violate the TSCs -- 3.4 Extracting the Timing Information of an OpenMP Program -- 3.4.1 Parallel Structure Stage -- 3.4.1.1 Parallel control flow analysis -- 3.4.1.2 Induction variables analysis -- 3.4.1.3 Reaching definitions and range analysis -- 3.4.1.4 Putting all together: The wave-front example -- 3.4.2 Task Expansion Stage -- 3.4.2.1 Control flow expansion and synchronization predicate resolution -- 3.4.2.2 tid: A unique task instance identifier -- 3.4.2.3 Missing information when deriving the DAG -- 3.4.3 Compiler Complexity -- 3.5 Summary -- References -- Chapter 4 - Mapping, Scheduling, and Schedulability Analysis -- 4.1 Introduction -- 4.2 System Model -- 4.3 Partitioned Scheduler -- 4.3.1 The Optimality of EDF on Preemptive Uniprocessors -- 4.3.2 FP-scheduling Algorithms -- 4.3.3 Limited Preemption Scheduling -- 4.3.4 Limited Preemption Schedulability Analysis -- 4.4 Global Scheduler with Migration Support -- 4.4.1 Migration-based Scheduler -- 4.4.2 Putting All Together -- 4.4.3 Implementation of a Limited Preemption Scheduler -- 4.5 Overall Schedulability Analysis -- 4.5.1 Model Formalization -- 4.5.2 Critical Interference of cp-tasks -- 4.5.3 Response Time Analysis -- 4.5.3.1 Inter-task interference -- 4.5.3.2 Intra-task interference -- 4.5.3.3 Computation of cp-task parameters -- 4.5.4 Non-conditional DAG Tasks -- 4.5.5 Series-Parallel Conditional DAG Tasks -- 4.5.6 Schedulability Condition -- 4.6 Specializing Analysis for Limited Pre-emption Global/Dynamic Approach -- 4.6.1 Blocking Impact of the Largest NPRs (LP-max).

4.6.2 Blocking Impact of the Largest Parallel NPRs (LP-ILP) -- 4.6.2.1 LP worst-case workload of a task executing on c cores -- 4.6.2.2 Overall LP worst-case workload -- 4.6.2.3 Lower-priority interference -- 4.6.3 Computation of Response Time Factors of LP-ILP -- 4.6.3.1 Worst-case workload of ˝ i executing on c cores: i[c] -- 4.6.3.2 Overall LP worst-case workload of lp(k) per executionscenario sl: ˆk[sl] -- 4.6.4 Complexity -- 4.7 Specializing Analysis for the Partitioned/Static Approach -- 4.7.1 ILP Formulation -- 4.7.1.1 Tied tasks -- 4.7.1.2 Untied tasks -- 4.7.1.3 Complexity -- 4.7.2 Heuristic Approaches -- 4.7.2.1 Tied tasks -- 4.7.2.2 Untied tasks -- 4.7.3 Integrating Interference from Additional RT Tasks -- 4.7.4 Critical Instant -- 4.7.5 Response-time Upper Bound -- 4.8 Scheduling for I/O Cores -- 4.9 Summary -- References -- Chapter 5 - Timing Analysis Methodology -- 5.1 Introduction -- 5.1.1 Static WCET Analysis Techniques -- 5.1.2 Measurement-based WCET Analysis Techniques -- 5.1.3 Hybrid WCET Techniques -- 5.1.4 Measurement-based Probabilistic Techniques -- 5.2 Our Choice of Methodology for WCET Estimation -- 5.2.1 Why Not Use Static Approaches? -- 5.2.2 Why Use Measurement-based Techniques? -- 5.3 Description of Our Timing Analysis Methodology -- 5.3.1 Intrinsic vs. Extrinsic Execution Times -- 5.3.2 The Concept of Safety Margins -- 5.3.3 Our Proposed Timing Methodology at a Glance -- 5.3.4 Overview of the Application Structure -- 5.3.5 Automatic Insertion and Removal of the Trace-points -- 5.3.5.1 How to insert the trace-points -- 5.3.5.2 How to remove the trace-points -- 5.3.6 Extract the Intrinsic Execution Time: The Isolation Mode -- 5.3.7 Extract the Extrinsic Execution Time: The Contention Mode -- 5.3.8 Extract the Execution Time in Real Situation: The Deployment Mode -- 5.3.9 Derive WCET Estimates -- 5.4 Summary -- References.

Chapter 6 - OpenMP Runtime -- 6.1 Introduction -- 6.2 Offloading Library Design -- 6.3 Tasking Runtime -- 6.3.1 Task Dependency Management -- 6.4 Experimental Results -- 6.4.1 Offloading Library -- 6.4.2 Tasking Runtime -- 6.4.2.1 Applications with a linear generation pattern -- 6.4.2.2 Applications with a recursive generation pattern -- 6.4.2.3 Applications with mixed patterns -- 6.4.2.4 Impact of cutoff on LINEAR and RECURSIVE applications -- 6.4.2.5 Real applications -- 6.4.3 Evaluation of the Task Dependency Mechanism -- 6.4.3.1 Performance speedup and memory usage -- 6.4.3.2 The task dependency mechanism on the MPPA -- 6.5 Summary -- References -- Chapter 7 - Embedded Operating Systems -- 7.1 Introduction -- 7.2 State of The Art -- 7.2.1 Real-time Support in Linux -- 7.2.1.1 Hard real-time support -- 7.2.1.2 Latency reduction -- 7.2.1.3 Real-time CPU scheduling -- 7.2.2 Survey of Existing Embedded RTOSs -- 7.2.3 Classification of Embedded RTOSs -- 7.3 Requirements for The Choice of The Run Time System -- 7.3.1 Programming Model -- 7.3.2 Preemption Support -- 7.3.3 Migration Support -- 7.3.4 Scheduling Characteristics -- 7.3.5 Timing Analysis -- 7.4 RTOS Selection -- 7.4.1 Host Processor -- 7.4.2 Manycore Processor -- 7.5 Operating System Support -- 7.5.1 Linux -- 7.5.2 ERIKA Enterprise Support -- 7.5.2.1 Exokernel support -- 7.5.2.2 Single-ELF multicore ERIKA Enterprise -- 7.5.2.3 Support for limited preemption, job, and global scheduling -- 7.5.2.4 New ERIKA Enterprise primitives -- 7.5.2.5 New data structures -- 7.5.2.6 Dynamic task creation -- 7.5.2.7 IRQ handlers as tasks -- 7.5.2.8 File hierarchy -- 7.5.2.9 Early performance estimation -- 7.6 Summary -- References -- Index -- About the Editors -- Back Cover.