Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design make...

Full description

Saved in:
Bibliographic Details
:
Year of Publication:2019
Language:English
Physical Description:1 electronic resource (202 p.)
Tags: Add Tag
No Tags, Be the first to tag this record!
LEADER 04688nam-a2201189z--4500
001 993548097904498
005 20231214133308.0
006 m o d
007 cr|mn|---annan
008 202102s2019 xx |||||o ||| 0|eng d
020 |a 3-03921-011-4 
035 |a (CKB)4920000000094867 
035 |a (oapen)https://directory.doabooks.org/handle/20.500.12854/53550 
035 |a (EXLCZ)994920000000094867 
041 0 |a eng 
100 1 |a Grasser, Tibor  |4 auth 
245 1 0 |a Miniaturized Transistors 
260 |b MDPI - Multidisciplinary Digital Publishing Institute  |c 2019 
300 |a 1 electronic resource (202 p.) 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
520 |a What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications. 
546 |a English 
653 |a MOSFET 
653 |a total ionizing dose (TID) 
653 |a low power consumption 
653 |a process simulation 
653 |a two-dimensional material 
653 |a negative-capacitance 
653 |a power consumption 
653 |a technology computer aided design (TCAD) 
653 |a thin-film transistors (TFTs) 
653 |a band-to-band tunneling (BTBT) 
653 |a nanowires 
653 |a inversion channel 
653 |a metal oxide semiconductor field effect transistor (MOSFET) 
653 |a spike-timing-dependent plasticity (STDP) 
653 |a field effect transistor 
653 |a segregation 
653 |a systematic variations 
653 |a Sentaurus TCAD 
653 |a indium selenide 
653 |a nanosheets 
653 |a technology computer-aided design (TCAD) 
653 |a high-? dielectric 
653 |a subthreshold bias range 
653 |a statistical variations 
653 |a fin field effect transistor (FinFET) 
653 |a compact models 
653 |a non-equilibrium Green's function 
653 |a etching simulation 
653 |a highly miniaturized transistor structure 
653 |a compact model 
653 |a silicon nanowire 
653 |a surface potential 
653 |a Silicon-Germanium source/drain (SiGe S/D) 
653 |a nanowire 
653 |a plasma-aided molecular beam epitaxy (MBE) 
653 |a phonon scattering 
653 |a mobility 
653 |a silicon-on-insulator 
653 |a drain engineered 
653 |a device simulation 
653 |a variability 
653 |a semi-floating gate 
653 |a synaptic transistor 
653 |a neuromorphic system 
653 |a theoretical model 
653 |a CMOS 
653 |a ferroelectrics 
653 |a tunnel field-effect transistor (TFET) 
653 |a SiGe 
653 |a metal gate granularity 
653 |a buried channel 
653 |a ON-state 
653 |a bulk NMOS devices 
653 |a ambipolar 
653 |a piezoelectrics 
653 |a tunnel field effect transistor (TFET) 
653 |a FinFETs 
653 |a polarization 
653 |a field-effect transistor 
653 |a line edge roughness 
653 |a random discrete dopants 
653 |a radiation hardened by design (RHBD) 
653 |a low energy 
653 |a flux calculation 
653 |a doping incorporation 
653 |a low voltage 
653 |a topography simulation 
653 |a MOS devices 
653 |a low-frequency noise 
653 |a high-k 
653 |a layout 
653 |a level set 
653 |a process variations 
653 |a subthreshold 
653 |a metal gate stack 
653 |a electrostatic discharge (ESD) 
776 |z 3-03921-010-6 
700 1 |a Filipovic, Lado  |4 auth 
906 |a BOOK 
ADM |b 2023-12-15 05:49:34 Europe/Vienna  |f system  |c marc21  |a 2019-11-10 04:18:40 Europe/Vienna  |g false 
AVE |i DOAB Directory of Open Access Books  |P DOAB Directory of Open Access Books  |x https://eu02.alma.exlibrisgroup.com/view/uresolver/43ACC_OEAW/openurl?u.ignore_date_coverage=true&portfolio_pid=5338701920004498&Force_direct=true  |Z 5338701920004498  |b Available  |8 5338701920004498