Computer Aided Verification : : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / / edited by Isil Dillig, Serdar Tasiran.
This open access two-volume set LNCS 11561 and 11562 constitutes the refereed proceedings of the 31st International Conference on Computer Aided Verification, CAV 2019, held in New York City, USA, in July 2019. The 52 full papers presented together with 13 tool papers and 2 case studies, were carefu...
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Place / Publishing House: | Cham : : Springer International Publishing :, Imprint: Springer,, 2019. |
Year of Publication: | 2019 |
Edition: | 1st ed. 2019. |
Language: | English |
Series: | Theoretical Computer Science and General Issues,
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Physical Description: | 1 online resource (XIX, 673 p. 1003 illus., 106 illus. in color.) |
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Dillig, Isil edt Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / edited by Isil Dillig, Serdar Tasiran. 1st ed. 2019. Cham : Springer International Publishing : Imprint: Springer, 2019. 1 online resource (XIX, 673 p. 1003 illus., 106 illus. in color.) text txt rdacontent computer c rdamedia online resource cr rdacarrier Theoretical Computer Science and General Issues, 2512-2029 ; 11561 English Automata and Timed Systems -- Symbolic Register Automata -- Abstraction Refinement Algorithms for Timed Automata -- Fast Algorithms for Handling Diagonal Constraints in Timed Automata -- Safety and co-safety comparator automata for discounted-sum inclusion -- Clock Bound Repair for Timed Systems -- Verifying Asynchronous Interactions via Communicating Session Automata -- Security and Hyperproperties -- Verifying Hyperliveness -- Quantitative Mitigation of Timing Side Channels -- Property Directed Self Composition -- Security-Aware Synthesis Using Delayed-Action Games -- Automated Hypersafety Verification -- Automated Synthesis of Secure Platform Mappings -- Synthesis -- Synthesizing Approximate Implementations for Unrealizable Specifications -- Quantified Invariants via Syntax-Guided Synthesis -- Efficient Synthesis with Probabilistic Constraints -- Membership-based Synthesis of Linear Hybrid Automata -- Overfitting in Synthesis: Theory and Practice -- Proving Unrealizability for Syntax-Guided Synthesis -- Model Checking -- BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings -- When Human Intuition Fails: Using Formal Methods to Find an Error in the "Proof" of a Multi-Agent Protocol -- Extending NUXMV with Timed Transition Systems and Timed Temporal Properties -- Cerberus-BMC: a Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C -- Cyber-physical Systems and Machine Learning -- Multi-Armed Bandits for Boolean Connectives in Hybrid System Falsification -- StreamLAB: Stream-based Monitoring of Cyber-Physical Systems -- VerifAI: A Toolkit for the Formal Design and Analysis of Artificial Intelligence-Based Systems -- The Marabou Framework for Verification and Analysis of Deep Neural Networks -- Probabilistic Systems, Runtime Techniques -- Probabilistic Bisimulation for Parameterized Systems -- Semi-Quantitative Abstraction and Analysis of Chemical Reaction Networks -- PAC Statistical Model Checking for Markov Decision Processes and Stochastic Games -- Symbolic Monitoring against Specifications Parametric in Time and Data -- STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis -- Dynamical, Hybrid, and Reactive Systems -- Local and Compositional Reasoning For Optimized Reactive Systems -- Robust Controller Synthesis in Timed Büchi Automata: A Symbolic Approach -- Flexible Computational Pipelines for Robust Abstraction-based Control Synthesis -- Temporal Stream Logic: Synthesis beyond the Bools -- Run-Time Optimization for Learned Controllers through Quantitative Games -- Taming Delays in Dynamical Systems: Unbounded Verification of Delay Differential Equations. This open access two-volume set LNCS 11561 and 11562 constitutes the refereed proceedings of the 31st International Conference on Computer Aided Verification, CAV 2019, held in New York City, USA, in July 2019. The 52 full papers presented together with 13 tool papers and 2 case studies, were carefully reviewed and selected from 258 submissions. The papers were organized in the following topical sections: Part I: automata and timed systems; security and hyperproperties; synthesis; model checking; cyber-physical systems and machine learning; probabilistic systems, runtime techniques; dynamical, hybrid, and reactive systems; Part II: logics, decision procedures; and solvers; numerical programs; verification; distributed systems and networks; verification and invariants; and concurrency. . Open Access Software engineering. Compilers (Computer programs). Computer science. Artificial intelligence. Computer simulation. Computer engineering. Computer networks. Software Engineering. Compilers and Interpreters. Theory of Computation. Artificial Intelligence. Computer Modelling. Computer Engineering and Networks. 3-030-25539-5 Dillig, Isil. editor. edt http://id.loc.gov/vocabulary/relators/edt Tasiran, Serdar. editor. edt http://id.loc.gov/vocabulary/relators/edt |
language |
English |
format |
eBook |
author2 |
Dillig, Isil. Dillig, Isil. Tasiran, Serdar. Tasiran, Serdar. |
author_facet |
Dillig, Isil. Dillig, Isil. Tasiran, Serdar. Tasiran, Serdar. |
author2_variant |
i d id i d id i d id s t st s t st |
author2_role |
HerausgeberIn HerausgeberIn HerausgeberIn HerausgeberIn |
author_sort |
Dillig, Isil. |
title |
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / |
spellingShingle |
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / Theoretical Computer Science and General Issues, Automata and Timed Systems -- Symbolic Register Automata -- Abstraction Refinement Algorithms for Timed Automata -- Fast Algorithms for Handling Diagonal Constraints in Timed Automata -- Safety and co-safety comparator automata for discounted-sum inclusion -- Clock Bound Repair for Timed Systems -- Verifying Asynchronous Interactions via Communicating Session Automata -- Security and Hyperproperties -- Verifying Hyperliveness -- Quantitative Mitigation of Timing Side Channels -- Property Directed Self Composition -- Security-Aware Synthesis Using Delayed-Action Games -- Automated Hypersafety Verification -- Automated Synthesis of Secure Platform Mappings -- Synthesis -- Synthesizing Approximate Implementations for Unrealizable Specifications -- Quantified Invariants via Syntax-Guided Synthesis -- Efficient Synthesis with Probabilistic Constraints -- Membership-based Synthesis of Linear Hybrid Automata -- Overfitting in Synthesis: Theory and Practice -- Proving Unrealizability for Syntax-Guided Synthesis -- Model Checking -- BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings -- When Human Intuition Fails: Using Formal Methods to Find an Error in the "Proof" of a Multi-Agent Protocol -- Extending NUXMV with Timed Transition Systems and Timed Temporal Properties -- Cerberus-BMC: a Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C -- Cyber-physical Systems and Machine Learning -- Multi-Armed Bandits for Boolean Connectives in Hybrid System Falsification -- StreamLAB: Stream-based Monitoring of Cyber-Physical Systems -- VerifAI: A Toolkit for the Formal Design and Analysis of Artificial Intelligence-Based Systems -- The Marabou Framework for Verification and Analysis of Deep Neural Networks -- Probabilistic Systems, Runtime Techniques -- Probabilistic Bisimulation for Parameterized Systems -- Semi-Quantitative Abstraction and Analysis of Chemical Reaction Networks -- PAC Statistical Model Checking for Markov Decision Processes and Stochastic Games -- Symbolic Monitoring against Specifications Parametric in Time and Data -- STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis -- Dynamical, Hybrid, and Reactive Systems -- Local and Compositional Reasoning For Optimized Reactive Systems -- Robust Controller Synthesis in Timed Büchi Automata: A Symbolic Approach -- Flexible Computational Pipelines for Robust Abstraction-based Control Synthesis -- Temporal Stream Logic: Synthesis beyond the Bools -- Run-Time Optimization for Learned Controllers through Quantitative Games -- Taming Delays in Dynamical Systems: Unbounded Verification of Delay Differential Equations. |
title_sub |
31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / |
title_full |
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / edited by Isil Dillig, Serdar Tasiran. |
title_fullStr |
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / edited by Isil Dillig, Serdar Tasiran. |
title_full_unstemmed |
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / edited by Isil Dillig, Serdar Tasiran. |
title_auth |
Computer Aided Verification : 31st International Conference, CAV 2019, New York City, NY, USA, July 15-18, 2019, Proceedings, Part I / |
title_new |
Computer Aided Verification : |
title_sort |
computer aided verification : 31st international conference, cav 2019, new york city, ny, usa, july 15-18, 2019, proceedings, part i / |
series |
Theoretical Computer Science and General Issues, |
series2 |
Theoretical Computer Science and General Issues, |
publisher |
Springer International Publishing : Imprint: Springer, |
publishDate |
2019 |
physical |
1 online resource (XIX, 673 p. 1003 illus., 106 illus. in color.) |
edition |
1st ed. 2019. |
contents |
Automata and Timed Systems -- Symbolic Register Automata -- Abstraction Refinement Algorithms for Timed Automata -- Fast Algorithms for Handling Diagonal Constraints in Timed Automata -- Safety and co-safety comparator automata for discounted-sum inclusion -- Clock Bound Repair for Timed Systems -- Verifying Asynchronous Interactions via Communicating Session Automata -- Security and Hyperproperties -- Verifying Hyperliveness -- Quantitative Mitigation of Timing Side Channels -- Property Directed Self Composition -- Security-Aware Synthesis Using Delayed-Action Games -- Automated Hypersafety Verification -- Automated Synthesis of Secure Platform Mappings -- Synthesis -- Synthesizing Approximate Implementations for Unrealizable Specifications -- Quantified Invariants via Syntax-Guided Synthesis -- Efficient Synthesis with Probabilistic Constraints -- Membership-based Synthesis of Linear Hybrid Automata -- Overfitting in Synthesis: Theory and Practice -- Proving Unrealizability for Syntax-Guided Synthesis -- Model Checking -- BMC for Weak Memory Models: Relation Analysis for Compact SMT Encodings -- When Human Intuition Fails: Using Formal Methods to Find an Error in the "Proof" of a Multi-Agent Protocol -- Extending NUXMV with Timed Transition Systems and Timed Temporal Properties -- Cerberus-BMC: a Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C -- Cyber-physical Systems and Machine Learning -- Multi-Armed Bandits for Boolean Connectives in Hybrid System Falsification -- StreamLAB: Stream-based Monitoring of Cyber-Physical Systems -- VerifAI: A Toolkit for the Formal Design and Analysis of Artificial Intelligence-Based Systems -- The Marabou Framework for Verification and Analysis of Deep Neural Networks -- Probabilistic Systems, Runtime Techniques -- Probabilistic Bisimulation for Parameterized Systems -- Semi-Quantitative Abstraction and Analysis of Chemical Reaction Networks -- PAC Statistical Model Checking for Markov Decision Processes and Stochastic Games -- Symbolic Monitoring against Specifications Parametric in Time and Data -- STAMINA: STochastic Approximate Model-checker for INfinite-state Analysis -- Dynamical, Hybrid, and Reactive Systems -- Local and Compositional Reasoning For Optimized Reactive Systems -- Robust Controller Synthesis in Timed Büchi Automata: A Symbolic Approach -- Flexible Computational Pipelines for Robust Abstraction-based Control Synthesis -- Temporal Stream Logic: Synthesis beyond the Bools -- Run-Time Optimization for Learned Controllers through Quantitative Games -- Taming Delays in Dynamical Systems: Unbounded Verification of Delay Differential Equations. |
isbn |
3-030-25540-9 3-030-25539-5 |
issn |
2512-2029 ; |
callnumber-first |
Q - Science |
callnumber-subject |
QA - Mathematics |
callnumber-label |
QA76 |
callnumber-sort |
QA 276.758 |
illustrated |
Not Illustrated |
dewey-hundreds |
000 - Computer science, information & general works |
dewey-tens |
000 - Computer science, knowledge & systems |
dewey-ones |
005 - Computer programming, programs & data |
dewey-full |
005.1 |
dewey-sort |
15.1 |
dewey-raw |
005.1 |
dewey-search |
005.1 |
oclc_num |
1132420999 |
work_keys_str_mv |
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