Interface design for hardware-in-the-loop simulation of real-time systems / Martin Schlager
ger: Hardware-in-the-Loop (HiL) simulation is a testing technique in which the environment of an (embedded) System-Under-Test (SUT) is simulated by an assigned HiL simulator. Thereby, the SUT interacts with the HiL simulator via the SUT's interface with its environment. The interaction between...
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| VerfasserIn: | |
|---|---|
| Place / Publishing House: | 2007 |
| Year of Publication: | 2007 |
| Language: | English |
| Subjects: | |
| Classification: | 54.76 - Computersimulation 54.32 - Rechnerkommunikation 54.39 - Systemarchitektur: Sonstiges 54.52 - Software engineering |
| Online Access: | |
| Physical Description: | XVI, 140 S.; Ill., graph. Darst. |
| Notes: | Zsfassung in dt. Sprache |
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| Location: | BASIS-Monographies |
| Call Numbers: | 36384-C.Stip. |
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| 36384-C.Stip. | BASIS-Monographies | Loan | Available | Place a Hold |