A Hands-On Guide to Designing Embedded Systems.

A Hands-On Guide to Designing Embedded Systems.

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Bibliographic Details
:
Taylor, Adam.
TeilnehmendeR:
Binnun, Dan.
Srivastava, Saket.
Place / Publishing House:Norwood : : Artech House,, 2021.
©2021.
Year of Publication:2021
Edition:1st ed.
Language:English
Online Access:
Physical Description:1 online resource (269 pages)
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Table of Contents:
  • Intro
  • A Hands-On Guide to Designing Embedded Systems
  • Contents
  • Acknowledgments
  • Introduction
  • CHAPTER 1 Programmatic and System-Level Considerations
  • 1.1 Introduction: SensorsThink
  • 1.2 Product Development Stages
  • 1.3 Product Development Stages: Tailoring
  • 1.4 Product Development: After Launch
  • 1.5 Requirements
  • 1.5.1 The V-Model
  • 1.5.2 SensorsThink: Product Requirements
  • 1.5.3 Creating Useful Requirements
  • 1.5.4 Requirements: Finishing Up
  • 1.6 Architectural Design
  • 1.6.1 SEBOK: An Invaluable Resource
  • 1.6.2 SensorsThink: Back to the Journey
  • 1.6.3 Systems Engineering: An Overview
  • 1.6.4 Architecting the System, Logically
  • 1.6.5 Keep Things in Context (Diagrams)
  • 1.6.6 Monitor Your Activity (Diagrams)
  • 1.6.7 Know the Proper Sequence (Diagrams)
  • 1.6.8 Architecting the System Physically
  • 1.6.9 Physical Architecture: Playing with Blocks
  • 1.6.10 Trace Your Steps
  • 1.6.11 System Verification and Validation: Check Your Work
  • 1.7 Engineering Budgets
  • 1.7.1 Types of Budgets
  • 1.7.2 Engineering Budgets: Some Examples
  • 1.7.3 Engineering Budgets: Finishing Up
  • 1.8 Interface Control Documents
  • 1.8.1 Sticking Together: Signal Grouping
  • 1.8.2 Playing with Legos: Connectorization
  • 1.8.3 Talking Among Yourselves: Internal ICDs
  • 1.9 Verification
  • 1.9.1 Verifying Hardware
  • 1.9.2 How Much Testing Is Enough?
  • 1.9.3 Safely Navigating the World of Testing
  • 1.9.4 A Deeper Dive into Derivation (of Test Cases)
  • 1.10 Engineering Governance
  • 1.10.1 Not Just Support for Design Reviews
  • 1.10.2 Engineering Rule Sets
  • 1.10.3 Compliance
  • 1.10.4 Review Meetings
  • References
  • CHAPTER 2 Hardware Design Considerations
  • 2.1 Component Selection
  • 2.1.1 Key Component Identification for the SoC Platform
  • 2.1.2 Key Component Selection Example: The SoC.
  • 2.1.3 Key Component Selection Example: Infrared Sensor
  • 2.1.4 Key Component Selection: Finishing Up
  • 2.2 Hardware Architecture
  • 2.2.1 Hardware Architecture for the SoC Platform
  • 2.2.2 Hardware Architecture: Interfaces
  • 2.2.3 Hardware Architecture: Data Flows
  • 2.2.4 Hardware Architecture: Finishing Up
  • 2.3 Designing the System
  • 2.3.1 What to Worry About
  • 2.3.2 Power Supply Analysis, Architecture, and Simulation
  • 2.3.3 Processor and FPGA Pinout Assignments
  • 2.3.4 System Clocking Requirements
  • 2.3.5 System Reset Requirements
  • 2.3.6 System Programming Scheme
  • 2.3.7 Summary
  • 2.3.8 Example: Zynq Power Sequence Requirements
  • 2.4 Decoupling your Components
  • 2.4.1 Decoupling: By the Book
  • 2.4.2 To Understand the Component, You Must Be the Component
  • 2.4.3 Types of Decoupling
  • 2.4.4 Example: Zynq-7000 Decoupling
  • 2.4.5 Additional Thoughts: Specialized Decoupling
  • 2.4.6 Additional Thoughts: Simulation
  • 2.5 Connect with Your System
  • 2.5.1 Contemplating Connectors
  • 2.5.2 Example: System Communications
  • 2.6 Extend the Life of the System: De-Rate
  • 2.6.1 Why De-Rate?
  • 2.6.2 What Can Be De-Rated?
  • 2.6.3 Example: De-Rating the Zynq-7000
  • 2.6.4 Additional Thoughts: Exceptions to the Rule
  • 2.7 Test, Test, Test
  • 2.7.1 Back to Basics: Pre-Power-On Checklist
  • 2.7.2 Check for Signs of Life: Crawl Before Walking
  • 2.7.3 Roll Up Your Sleeves and Get Ready to Run
  • 2.7.4 Example: I2C Interface
  • 2.7.5 Additional Thoughts
  • 2.8 Integrity: Important for Electronics
  • 2.8.1 Power Integrity
  • 2.8.2 Signal Integrity
  • 2.8.3 Digging Deeper into Power Integrity
  • 2.8.4 Digging Deeper into Signal Integrity
  • 2.8.5 Example: ULPI Pre-Layout Analysis
  • 2.8.6 Suggested Additional Reading
  • 2.9 PCB Layout: Not for the Faint of Heart
  • 2.9.1 Floor Planning
  • 2.9.2 Follow the Rats
  • 2.9.3 Mechanical Constraints.
  • 2.9.4 Electrical Constraints
  • 2.9.5 Stack-Up Design
  • 2.9.6 Experience Matters
  • References
  • CHAPTER 3 FPGA Design Considerations
  • 3.1 Introduction
  • 3.2 FPGA Development Process
  • 3.2.1 Introduction to the Target Device
  • 3.2.2 FPGA Requirements
  • 3.2.3 FPGA Architecture
  • 3.3 Accelerating Design Using IP Libraries
  • 3.4 Pin Planning and Constraints
  • 3.4.1 Physical Constraints
  • 3.4.2 Timing Constraints
  • 3.4.3 Timing Exceptions
  • 3.4.4 Physical Constraints: Placement
  • 3.5 Clock Domain Crossing
  • 3.6 Test Bench and Verification
  • 3.6.1 What Is Verification?
  • 3.6.2 Self-Checking Test Benches
  • 3.6.3 Corner Cases, Boundary Conditions, and Stress Testing
  • 3.6.4 Code Coverage
  • 3.6.5 Test Functions and Procedures
  • 3.6.6 Behavioral Models
  • 3.6.7 Using Text IO Files
  • 3.6.8 What Else Might We Consider?
  • 3.7 Finite State Machine Design
  • 3.7.1 Defining a State Machine
  • 3.7.2 Algorithmic State Diagrams
  • 3.7.3 Moore or Mealy: What Should I Choose?
  • 3.7.4 Implementing the State Machine
  • 3.7.5 State Machine Encoding
  • 3.7.6 Increasing Performance of State Machines
  • 3.7.7 Good Design Practices for FPGA Implementation
  • 3.7.8 FLIR Lepton Interface
  • 3.8 Defensive State Machine Design
  • 3.8.1 Detection Schemes
  • 3.8.2 Hamming Schemes
  • 3.8.3 Deadlock and Other Issues
  • 3.8.4 Implementing Defensive State Machines in Xilinx Devices
  • 3.9 How Does FPGA Do Math?
  • 3.9.1 Representation of Numbers
  • 3.10 Fixed Point Mathematics
  • 3.10.1 Fixed-Point Rules
  • 3.10.2 Overflow
  • 3.10.3 Real-World Implementation
  • 3.10.4 RTL Implementation
  • 3.11 Polynomial Approximation
  • 3.11.1 The Challenge with Some Algorithms
  • 3.11.2 Capitalize on FPGA Resources
  • 3.11.3 Multiple Trend Lines Selected by Input Value
  • 3.12 The CORDIC Algorithm
  • 3.13 Convergence
  • 3.14 Where Are These Used
  • 3.15 Modeling in Excel.
  • 3.16 Implementing the CORDIC
  • 3.17 Digital Filter Design and Implementation
  • 3.17.1 Filter Types and Topologies
  • 3.17.2 Frequency Response
  • 3.17.3 Impulse Response
  • 3.17.4 Step Response
  • 3.17.5 Windowing the Filter
  • 3.18 Fast Fourier Transforms
  • 3.18.1 Time or Frequency Domain?
  • 3.19 How Do We Get There?
  • 3.19.1 Where Do We Use These?
  • 3.19.2 FPGA-Based Implementation
  • 3.19.3 Higher-Speed Sampling
  • 3.20 Working with ADC and DAC
  • 3.20.1 ADC and DAC Key Parameters
  • 3.20.2 The Frequency Spectrum
  • 3.20.3 Communication
  • 3.20.4 DAC Filtering
  • 3.20.5 In-System Test
  • 3.21 High-Level Synthesis
  • CHAPTER 4 When Reliability Counts
  • 4.1 Introduction to Reliability
  • 4.2 Mathematical Interpretation of System Reliability
  • 4.2.1 The Bathtub Curve
  • 4.2.2  Failure Rate (λ)
  • 4.2.3 Early Life Failure Rate
  • 4.2.4 Key Terms
  • 4.2.5 Repairable and Nonrepairable Systems
  • 4.2.6 MTTF, MTBF, and MTTR
  • 4.2.7 Maintainability
  • 4.2.8 Availability
  • 4.3 Calculating System Reliability
  • 4.3.1 Scenario 1: All Critical Components Connected in Series
  • 4.3.2 Scenario 2: All Critical Components Connected in Parallel
  • 4.3.3 Scenario 3: All Critical Components Are Connected in Series-Parallel Configuration
  • 4.4 Faults, Errors, and Failure
  • 4.4.1 Classification of Faults
  • 4.4.2 Fault Prevention Versus Fault Tolerance: Which One Can Address System Failure Better?
  • 4.5 Fault Tolerance Techniques
  • 4.5.1 Redundancy Technique for Hardware Fault Tolerance
  • 4.5.2 Software Fault Tolerance
  • 4.6 Worst-Case Circuit Analysis
  • 4.6.1 Sources of Variation
  • 4.6.2 Numerical Analysis Using SPICE Modeling
  • Selected Bibliography
  • About the Authors
  • Index.

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