Embedded Firmware Solutions : : Development Best Practices for the Internet of Things.
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Place / Publishing House: | Berkeley, CA : : Apress L. P.,, 2015. ©2015. |
Year of Publication: | 2015 |
Edition: | 1st ed. |
Language: | English |
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Physical Description: | 1 online resource (215 pages) |
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Zimmer, Vincent. Embedded Firmware Solutions : Development Best Practices for the Internet of Things. 1st ed. Berkeley, CA : Apress L. P., 2015. ©2015. 1 online resource (215 pages) text txt rdacontent computer c rdamedia online resource cr rdacarrier Intro -- Contents at a Glance -- Contents -- About the Authors -- About the Technical Reviewers -- Acknowledgments -- Foreword -- Introduction -- Chapter 1: Introduction -- What Is Embedded Firmware? -- Where Is Firmware? -- What Do Firmware Engineers Do? -- Firmware Preparation for New Hardware -- The Mystery of Bits -- Programming Guides -- The Intel® Firmware Support Package -- The Uniqueness of Embedded Firmware -- The Choice of Firmware Stacks -- Welcome to the Era of the Internet of Things -- Technical Coverage in This Book -- The Future of Firmware -- Chapter 2: Firmware Stacks for Embedded Systems -- Is a One-Size-Fits-All Solution Possible? -- Microkernel -- Real-Time Operating S ystem (RTOS) -- Legacy BIOS -- Implementations of the UEFI Framework -- Open Source Firmware Stacks -- Proprietary Firmware Stacks -- Make o r Buy -- The Advantages of Outsourcing -- The Disadvantages of Outsourcing -- In-House Development -- Summary -- Chapter 3: Intel® Firmware Support Package (Intel® FSP) -- The Intel FSP Philosophy -- What Is in Intel FSP? -- Intel FSP Binary Format -- Sample Boot Flow -- Locating the Entries of Intel FSP -- The Hard Way to Find Intel FSP APIs: Use Data Structure -- The Easy Way to Find FSP APIs: Use Hard-Coded Constants -- Programming Interface: The APIs of Intel FSP -- TempRamInit -- FspInitEntry -- NotifyPhase -- Intel FSP Output -- API Execution Status -- Temporary Memory Data HOB -- Non-Volatile Storage HOB -- Sample Code for Parsing HOBs -- Customization of Intel FSP -- Downloading Intel FSP -- Microcode Patches -- Relocating Intel FSP -- Integration and Build -- The Future of Intel FSP -- What Is Coming in the Following Chapters -- Chapter 4: Building coreboot with Intel FSP -- The Introduction of coreboot -- The Philosophy of coreboot -- A Brief History -- v1: 1999-2000 -- v2: 2000-2005 -- v2+: 2005-2008. v3: 2006-2008 -- 2008 LinuxBIOS Renamed "coreboot" -- v4: 2009-2012 -- v4+: 2012-2014 -- Further Reading -- Prerequisites for Working with coreboot -- Community Organization -- Git and Gerrit -- Git Commit Messages -- coreboot Sign-off Procedure -- Developer's Certificate of Origin 1.1 -- Adding Your Sign-off -- Working with the coreboot Community -- coreboot Do's -- coreboot Don'ts -- Nonsource Binaries in coreboot -- A Hands-on Example: Building coreboot for the MinnowBoard MAX Mainboard -- Environment -- Hardware: MinnowBoard MAX -- MinnowBoard MAX Platform Details -- Development Directory -- Downloading Intel FSP -- Installing Intel FSP -- Downloading the coreboot Source -- coreboot Toolchain -- coreboot Commit Hooks -- Creating a coreboot Development Branch -- Building the Mainboard -- On the Menuconfig Menu -- On the Chipset Menu -- On the Devices Menu -- Build -- Summary of Commands -- Flashing the ROM -- Preparing the Flash Programmer -- Flashing the ROM Image -- coreboot Internals -- Boot Stages -- Additional Files -- CBFS -- An Example of CBFS -- CBFS Size -- Special Binaries -- Boot Flow Using Intel FSP -- Reset Vector and Bootblock -- romstage -- ramstage -- Payload -- coreboot Source -- coreboot Device Tree -- Chips and Devices -- Device Tree Variables -- A Device Tree Example -- Chip Operations -- Device Operations -- coreboot Hardwaremain State Machine -- State Machine States -- State Machine Callbacks -- Mainboard -- The Chipset Driver -- Chipset FSP UPD Options -- The FSP Driver -- Kconfig -- xcompile -- Payloads -- SeaBIOS -- GRUB 2 -- FILO -- iPXE -- TianoCore -- Depthcharge -- U- Boot -- Memtest86+ -- libpayload -- coreboot Troubleshooting and Debugging -- Postcodes -- Serial Debug -- EHCI USB Debug -- Summary -- Chapter 5: Chrome book Firmware Internals -- About Chrome book and Chrome OS -- Chrome OS Firmware Overview. Chrome OS Security Philosophy -- Chrome OS Security Guiding Principles -- Power wash -- Chrome OS Boot Modes -- Verified (Normal) Mode -- Recovery Mode -- Developer Mode -- Chrome OS Coreboot -- x86 -- ARM -- Depth charge Payload -- libpayload -- Verified Boot -- Verified Boot and Kernel Security -- Chrome OS Firmware Boot Log -- Boot Times Log -- Chrome OS Firmware Event Log -- Google SMI Linux Kernel Driver -- Chrome OS Extensions to the Firmware Image -- FMAP -- BOOT_STUB FMAP Section -- Chrome OS Firmware RW FMAP Sections -- An fmap.dts (RW_SECTION_A) Example -- Google Binary Block (GBB) -- GBB: HWID v3 -- GBB: Firmware Bitmaps -- GBB: Firmware Keys -- GBB: Boot Flags -- Vital Product Data ( VPD) -- Firmware TPM Usage -- Chrome OS Firmware Update -- Chrome OS Utilities -- flashrom -- gbb_utility -- GBB Flags Utility Script: set_gbb_flags.sh -- crossystem -- mosys -- Google Embedded Controller -- Power Sequencing -- Battery Charging -- Thermal Management -- Keyboard Controller -- Other Peripheral Controls -- Chrome EC Software Sync -- Software Sync Steps -- Summary -- Chapter 6: Intel FSP and UEFI Integration -- Introduction to EFI -- Introduction to FSP -- Introduction to EDK II -- Summary -- FSP Components -- FSP Wrapper Boot Flow -- Generic FSP Wrapper Boot Flow -- Normal Boot -- Boot Flow -- Memory Layout for a Normal Boot Flow -- FSP Normal Boot Data Structure -- S3 Boot -- Boot Flow -- S3 Memory Layout -- S3 NV Data Passing -- Capsule Flash Update -- Boot Flow -- Capsule Update Memory Layout -- Recovery Boot Flow -- FSP Recovery Memory Layout -- coreboot Payload Based upon EDK II -- Building Minnow and MinnowMax with FSP -- Future of the Intel FSP -- Conclusion -- Chapter 7: Building Firmware for Quark Processors -- Overview of UEFI and PI -- History of Implementations and Specifications -- Introduction to EDK II Building Blocks. PKG: Packaging -- MdePkg -- MdeModulePkg -- IntelFrameworkPkg -- IntelFrameworkModulePkg -- Packages -- PCD: Platform Configuration Database -- Syntax -- DEC: Platform Declaration File -- Syntax -- DSC: Platform Description File -- FDF: Flash Description File -- Syntax -- Build: The EDK II Build Command -- INF: INF File -- More Information -- Introduction to the EDK II Subset -- Introduction to Quark -- ROM Flash Image Size Optimization -- Fixed Resource -- DRAM/SMRAM -- Remove Features -- Reduce Features -- Compiler Options -- Build Options -- Results of the TinyQuark Optimization -- RAM Footprint Optimization -- Optimization -- Result of Memory Usage Optimization -- Conclusion -- Chapter 8: Putting It All Together -- RTOS and Intel FSP -- Intel FSP and Open Source Philosophy -- Customization and Production of Intel FSP -- It Is a Community Effort After All -- Appendix A: Sample Boot Setting File (BSF) -- Index. Description based on publisher supplied metadata and other sources. Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. Electronic books. Sun, Jiming. Jones, Marc. Reinauer, Stefan. Print version: Zimmer, Vincent Embedded Firmware Solutions Berkeley, CA : Apress L. P.,c2015 9781484200711 ProQuest (Firm) https://ebookcentral.proquest.com/lib/oeawat/detail.action?docID=6422674 Click to View |
language |
English |
format |
eBook |
author |
Zimmer, Vincent. |
spellingShingle |
Zimmer, Vincent. Embedded Firmware Solutions : Development Best Practices for the Internet of Things. Intro -- Contents at a Glance -- Contents -- About the Authors -- About the Technical Reviewers -- Acknowledgments -- Foreword -- Introduction -- Chapter 1: Introduction -- What Is Embedded Firmware? -- Where Is Firmware? -- What Do Firmware Engineers Do? -- Firmware Preparation for New Hardware -- The Mystery of Bits -- Programming Guides -- The Intel® Firmware Support Package -- The Uniqueness of Embedded Firmware -- The Choice of Firmware Stacks -- Welcome to the Era of the Internet of Things -- Technical Coverage in This Book -- The Future of Firmware -- Chapter 2: Firmware Stacks for Embedded Systems -- Is a One-Size-Fits-All Solution Possible? -- Microkernel -- Real-Time Operating S ystem (RTOS) -- Legacy BIOS -- Implementations of the UEFI Framework -- Open Source Firmware Stacks -- Proprietary Firmware Stacks -- Make o r Buy -- The Advantages of Outsourcing -- The Disadvantages of Outsourcing -- In-House Development -- Summary -- Chapter 3: Intel® Firmware Support Package (Intel® FSP) -- The Intel FSP Philosophy -- What Is in Intel FSP? -- Intel FSP Binary Format -- Sample Boot Flow -- Locating the Entries of Intel FSP -- The Hard Way to Find Intel FSP APIs: Use Data Structure -- The Easy Way to Find FSP APIs: Use Hard-Coded Constants -- Programming Interface: The APIs of Intel FSP -- TempRamInit -- FspInitEntry -- NotifyPhase -- Intel FSP Output -- API Execution Status -- Temporary Memory Data HOB -- Non-Volatile Storage HOB -- Sample Code for Parsing HOBs -- Customization of Intel FSP -- Downloading Intel FSP -- Microcode Patches -- Relocating Intel FSP -- Integration and Build -- The Future of Intel FSP -- What Is Coming in the Following Chapters -- Chapter 4: Building coreboot with Intel FSP -- The Introduction of coreboot -- The Philosophy of coreboot -- A Brief History -- v1: 1999-2000 -- v2: 2000-2005 -- v2+: 2005-2008. v3: 2006-2008 -- 2008 LinuxBIOS Renamed "coreboot" -- v4: 2009-2012 -- v4+: 2012-2014 -- Further Reading -- Prerequisites for Working with coreboot -- Community Organization -- Git and Gerrit -- Git Commit Messages -- coreboot Sign-off Procedure -- Developer's Certificate of Origin 1.1 -- Adding Your Sign-off -- Working with the coreboot Community -- coreboot Do's -- coreboot Don'ts -- Nonsource Binaries in coreboot -- A Hands-on Example: Building coreboot for the MinnowBoard MAX Mainboard -- Environment -- Hardware: MinnowBoard MAX -- MinnowBoard MAX Platform Details -- Development Directory -- Downloading Intel FSP -- Installing Intel FSP -- Downloading the coreboot Source -- coreboot Toolchain -- coreboot Commit Hooks -- Creating a coreboot Development Branch -- Building the Mainboard -- On the Menuconfig Menu -- On the Chipset Menu -- On the Devices Menu -- Build -- Summary of Commands -- Flashing the ROM -- Preparing the Flash Programmer -- Flashing the ROM Image -- coreboot Internals -- Boot Stages -- Additional Files -- CBFS -- An Example of CBFS -- CBFS Size -- Special Binaries -- Boot Flow Using Intel FSP -- Reset Vector and Bootblock -- romstage -- ramstage -- Payload -- coreboot Source -- coreboot Device Tree -- Chips and Devices -- Device Tree Variables -- A Device Tree Example -- Chip Operations -- Device Operations -- coreboot Hardwaremain State Machine -- State Machine States -- State Machine Callbacks -- Mainboard -- The Chipset Driver -- Chipset FSP UPD Options -- The FSP Driver -- Kconfig -- xcompile -- Payloads -- SeaBIOS -- GRUB 2 -- FILO -- iPXE -- TianoCore -- Depthcharge -- U- Boot -- Memtest86+ -- libpayload -- coreboot Troubleshooting and Debugging -- Postcodes -- Serial Debug -- EHCI USB Debug -- Summary -- Chapter 5: Chrome book Firmware Internals -- About Chrome book and Chrome OS -- Chrome OS Firmware Overview. Chrome OS Security Philosophy -- Chrome OS Security Guiding Principles -- Power wash -- Chrome OS Boot Modes -- Verified (Normal) Mode -- Recovery Mode -- Developer Mode -- Chrome OS Coreboot -- x86 -- ARM -- Depth charge Payload -- libpayload -- Verified Boot -- Verified Boot and Kernel Security -- Chrome OS Firmware Boot Log -- Boot Times Log -- Chrome OS Firmware Event Log -- Google SMI Linux Kernel Driver -- Chrome OS Extensions to the Firmware Image -- FMAP -- BOOT_STUB FMAP Section -- Chrome OS Firmware RW FMAP Sections -- An fmap.dts (RW_SECTION_A) Example -- Google Binary Block (GBB) -- GBB: HWID v3 -- GBB: Firmware Bitmaps -- GBB: Firmware Keys -- GBB: Boot Flags -- Vital Product Data ( VPD) -- Firmware TPM Usage -- Chrome OS Firmware Update -- Chrome OS Utilities -- flashrom -- gbb_utility -- GBB Flags Utility Script: set_gbb_flags.sh -- crossystem -- mosys -- Google Embedded Controller -- Power Sequencing -- Battery Charging -- Thermal Management -- Keyboard Controller -- Other Peripheral Controls -- Chrome EC Software Sync -- Software Sync Steps -- Summary -- Chapter 6: Intel FSP and UEFI Integration -- Introduction to EFI -- Introduction to FSP -- Introduction to EDK II -- Summary -- FSP Components -- FSP Wrapper Boot Flow -- Generic FSP Wrapper Boot Flow -- Normal Boot -- Boot Flow -- Memory Layout for a Normal Boot Flow -- FSP Normal Boot Data Structure -- S3 Boot -- Boot Flow -- S3 Memory Layout -- S3 NV Data Passing -- Capsule Flash Update -- Boot Flow -- Capsule Update Memory Layout -- Recovery Boot Flow -- FSP Recovery Memory Layout -- coreboot Payload Based upon EDK II -- Building Minnow and MinnowMax with FSP -- Future of the Intel FSP -- Conclusion -- Chapter 7: Building Firmware for Quark Processors -- Overview of UEFI and PI -- History of Implementations and Specifications -- Introduction to EDK II Building Blocks. PKG: Packaging -- MdePkg -- MdeModulePkg -- IntelFrameworkPkg -- IntelFrameworkModulePkg -- Packages -- PCD: Platform Configuration Database -- Syntax -- DEC: Platform Declaration File -- Syntax -- DSC: Platform Description File -- FDF: Flash Description File -- Syntax -- Build: The EDK II Build Command -- INF: INF File -- More Information -- Introduction to the EDK II Subset -- Introduction to Quark -- ROM Flash Image Size Optimization -- Fixed Resource -- DRAM/SMRAM -- Remove Features -- Reduce Features -- Compiler Options -- Build Options -- Results of the TinyQuark Optimization -- RAM Footprint Optimization -- Optimization -- Result of Memory Usage Optimization -- Conclusion -- Chapter 8: Putting It All Together -- RTOS and Intel FSP -- Intel FSP and Open Source Philosophy -- Customization and Production of Intel FSP -- It Is a Community Effort After All -- Appendix A: Sample Boot Setting File (BSF) -- Index. |
author_facet |
Zimmer, Vincent. Sun, Jiming. Jones, Marc. Reinauer, Stefan. |
author_variant |
v z vz |
author2 |
Sun, Jiming. Jones, Marc. Reinauer, Stefan. |
author2_variant |
j s js m j mj s r sr |
author2_role |
TeilnehmendeR TeilnehmendeR TeilnehmendeR |
author_sort |
Zimmer, Vincent. |
title |
Embedded Firmware Solutions : Development Best Practices for the Internet of Things. |
title_sub |
Development Best Practices for the Internet of Things. |
title_full |
Embedded Firmware Solutions : Development Best Practices for the Internet of Things. |
title_fullStr |
Embedded Firmware Solutions : Development Best Practices for the Internet of Things. |
title_full_unstemmed |
Embedded Firmware Solutions : Development Best Practices for the Internet of Things. |
title_auth |
Embedded Firmware Solutions : Development Best Practices for the Internet of Things. |
title_new |
Embedded Firmware Solutions : |
title_sort |
embedded firmware solutions : development best practices for the internet of things. |
publisher |
Apress L. P., |
publishDate |
2015 |
physical |
1 online resource (215 pages) |
edition |
1st ed. |
contents |
Intro -- Contents at a Glance -- Contents -- About the Authors -- About the Technical Reviewers -- Acknowledgments -- Foreword -- Introduction -- Chapter 1: Introduction -- What Is Embedded Firmware? -- Where Is Firmware? -- What Do Firmware Engineers Do? -- Firmware Preparation for New Hardware -- The Mystery of Bits -- Programming Guides -- The Intel® Firmware Support Package -- The Uniqueness of Embedded Firmware -- The Choice of Firmware Stacks -- Welcome to the Era of the Internet of Things -- Technical Coverage in This Book -- The Future of Firmware -- Chapter 2: Firmware Stacks for Embedded Systems -- Is a One-Size-Fits-All Solution Possible? -- Microkernel -- Real-Time Operating S ystem (RTOS) -- Legacy BIOS -- Implementations of the UEFI Framework -- Open Source Firmware Stacks -- Proprietary Firmware Stacks -- Make o r Buy -- The Advantages of Outsourcing -- The Disadvantages of Outsourcing -- In-House Development -- Summary -- Chapter 3: Intel® Firmware Support Package (Intel® FSP) -- The Intel FSP Philosophy -- What Is in Intel FSP? -- Intel FSP Binary Format -- Sample Boot Flow -- Locating the Entries of Intel FSP -- The Hard Way to Find Intel FSP APIs: Use Data Structure -- The Easy Way to Find FSP APIs: Use Hard-Coded Constants -- Programming Interface: The APIs of Intel FSP -- TempRamInit -- FspInitEntry -- NotifyPhase -- Intel FSP Output -- API Execution Status -- Temporary Memory Data HOB -- Non-Volatile Storage HOB -- Sample Code for Parsing HOBs -- Customization of Intel FSP -- Downloading Intel FSP -- Microcode Patches -- Relocating Intel FSP -- Integration and Build -- The Future of Intel FSP -- What Is Coming in the Following Chapters -- Chapter 4: Building coreboot with Intel FSP -- The Introduction of coreboot -- The Philosophy of coreboot -- A Brief History -- v1: 1999-2000 -- v2: 2000-2005 -- v2+: 2005-2008. v3: 2006-2008 -- 2008 LinuxBIOS Renamed "coreboot" -- v4: 2009-2012 -- v4+: 2012-2014 -- Further Reading -- Prerequisites for Working with coreboot -- Community Organization -- Git and Gerrit -- Git Commit Messages -- coreboot Sign-off Procedure -- Developer's Certificate of Origin 1.1 -- Adding Your Sign-off -- Working with the coreboot Community -- coreboot Do's -- coreboot Don'ts -- Nonsource Binaries in coreboot -- A Hands-on Example: Building coreboot for the MinnowBoard MAX Mainboard -- Environment -- Hardware: MinnowBoard MAX -- MinnowBoard MAX Platform Details -- Development Directory -- Downloading Intel FSP -- Installing Intel FSP -- Downloading the coreboot Source -- coreboot Toolchain -- coreboot Commit Hooks -- Creating a coreboot Development Branch -- Building the Mainboard -- On the Menuconfig Menu -- On the Chipset Menu -- On the Devices Menu -- Build -- Summary of Commands -- Flashing the ROM -- Preparing the Flash Programmer -- Flashing the ROM Image -- coreboot Internals -- Boot Stages -- Additional Files -- CBFS -- An Example of CBFS -- CBFS Size -- Special Binaries -- Boot Flow Using Intel FSP -- Reset Vector and Bootblock -- romstage -- ramstage -- Payload -- coreboot Source -- coreboot Device Tree -- Chips and Devices -- Device Tree Variables -- A Device Tree Example -- Chip Operations -- Device Operations -- coreboot Hardwaremain State Machine -- State Machine States -- State Machine Callbacks -- Mainboard -- The Chipset Driver -- Chipset FSP UPD Options -- The FSP Driver -- Kconfig -- xcompile -- Payloads -- SeaBIOS -- GRUB 2 -- FILO -- iPXE -- TianoCore -- Depthcharge -- U- Boot -- Memtest86+ -- libpayload -- coreboot Troubleshooting and Debugging -- Postcodes -- Serial Debug -- EHCI USB Debug -- Summary -- Chapter 5: Chrome book Firmware Internals -- About Chrome book and Chrome OS -- Chrome OS Firmware Overview. Chrome OS Security Philosophy -- Chrome OS Security Guiding Principles -- Power wash -- Chrome OS Boot Modes -- Verified (Normal) Mode -- Recovery Mode -- Developer Mode -- Chrome OS Coreboot -- x86 -- ARM -- Depth charge Payload -- libpayload -- Verified Boot -- Verified Boot and Kernel Security -- Chrome OS Firmware Boot Log -- Boot Times Log -- Chrome OS Firmware Event Log -- Google SMI Linux Kernel Driver -- Chrome OS Extensions to the Firmware Image -- FMAP -- BOOT_STUB FMAP Section -- Chrome OS Firmware RW FMAP Sections -- An fmap.dts (RW_SECTION_A) Example -- Google Binary Block (GBB) -- GBB: HWID v3 -- GBB: Firmware Bitmaps -- GBB: Firmware Keys -- GBB: Boot Flags -- Vital Product Data ( VPD) -- Firmware TPM Usage -- Chrome OS Firmware Update -- Chrome OS Utilities -- flashrom -- gbb_utility -- GBB Flags Utility Script: set_gbb_flags.sh -- crossystem -- mosys -- Google Embedded Controller -- Power Sequencing -- Battery Charging -- Thermal Management -- Keyboard Controller -- Other Peripheral Controls -- Chrome EC Software Sync -- Software Sync Steps -- Summary -- Chapter 6: Intel FSP and UEFI Integration -- Introduction to EFI -- Introduction to FSP -- Introduction to EDK II -- Summary -- FSP Components -- FSP Wrapper Boot Flow -- Generic FSP Wrapper Boot Flow -- Normal Boot -- Boot Flow -- Memory Layout for a Normal Boot Flow -- FSP Normal Boot Data Structure -- S3 Boot -- Boot Flow -- S3 Memory Layout -- S3 NV Data Passing -- Capsule Flash Update -- Boot Flow -- Capsule Update Memory Layout -- Recovery Boot Flow -- FSP Recovery Memory Layout -- coreboot Payload Based upon EDK II -- Building Minnow and MinnowMax with FSP -- Future of the Intel FSP -- Conclusion -- Chapter 7: Building Firmware for Quark Processors -- Overview of UEFI and PI -- History of Implementations and Specifications -- Introduction to EDK II Building Blocks. PKG: Packaging -- MdePkg -- MdeModulePkg -- IntelFrameworkPkg -- IntelFrameworkModulePkg -- Packages -- PCD: Platform Configuration Database -- Syntax -- DEC: Platform Declaration File -- Syntax -- DSC: Platform Description File -- FDF: Flash Description File -- Syntax -- Build: The EDK II Build Command -- INF: INF File -- More Information -- Introduction to the EDK II Subset -- Introduction to Quark -- ROM Flash Image Size Optimization -- Fixed Resource -- DRAM/SMRAM -- Remove Features -- Reduce Features -- Compiler Options -- Build Options -- Results of the TinyQuark Optimization -- RAM Footprint Optimization -- Optimization -- Result of Memory Usage Optimization -- Conclusion -- Chapter 8: Putting It All Together -- RTOS and Intel FSP -- Intel FSP and Open Source Philosophy -- Customization and Production of Intel FSP -- It Is a Community Effort After All -- Appendix A: Sample Boot Setting File (BSF) -- Index. |
isbn |
9781484200704 9781484200711 |
callnumber-first |
T - Technology |
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TS - Manufactures |
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TS171 |
callnumber-sort |
TS 3171.57 |
genre |
Electronic books. |
genre_facet |
Electronic books. |
url |
https://ebookcentral.proquest.com/lib/oeawat/detail.action?docID=6422674 |
illustrated |
Not Illustrated |
dewey-hundreds |
000 - Computer science, information & general works |
dewey-tens |
000 - Computer science, knowledge & systems |
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005 - Computer programming, programs & data |
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15.3 |
dewey-raw |
005.3 |
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P.,</subfield><subfield code="c">2015.</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">©2015.</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (215 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">computer</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">online resource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Intro -- Contents at a Glance -- Contents -- About the Authors -- About the Technical Reviewers -- Acknowledgments -- Foreword -- Introduction -- Chapter 1: Introduction -- What Is Embedded Firmware? -- Where Is Firmware? -- What Do Firmware Engineers Do? -- Firmware Preparation for New Hardware -- The Mystery of Bits -- Programming Guides -- The Intel® Firmware Support Package -- The Uniqueness of Embedded Firmware -- The Choice of Firmware Stacks -- Welcome to the Era of the Internet of Things -- Technical Coverage in This Book -- The Future of Firmware -- Chapter 2: Firmware Stacks for Embedded Systems -- Is a One-Size-Fits-All Solution Possible? -- Microkernel -- Real-Time Operating S ystem (RTOS) -- Legacy BIOS -- Implementations of the UEFI Framework -- Open Source Firmware Stacks -- Proprietary Firmware Stacks -- Make o r Buy -- The Advantages of Outsourcing -- The Disadvantages of Outsourcing -- In-House Development -- Summary -- Chapter 3: Intel® Firmware Support Package (Intel® FSP) -- The Intel FSP Philosophy -- What Is in Intel FSP? -- Intel FSP Binary Format -- Sample Boot Flow -- Locating the Entries of Intel FSP -- The Hard Way to Find Intel FSP APIs: Use Data Structure -- The Easy Way to Find FSP APIs: Use Hard-Coded Constants -- Programming Interface: The APIs of Intel FSP -- TempRamInit -- FspInitEntry -- NotifyPhase -- Intel FSP Output -- API Execution Status -- Temporary Memory Data HOB -- Non-Volatile Storage HOB -- Sample Code for Parsing HOBs -- Customization of Intel FSP -- Downloading Intel FSP -- Microcode Patches -- Relocating Intel FSP -- Integration and Build -- The Future of Intel FSP -- What Is Coming in the Following Chapters -- Chapter 4: Building coreboot with Intel FSP -- The Introduction of coreboot -- The Philosophy of coreboot -- A Brief History -- v1: 1999-2000 -- v2: 2000-2005 -- v2+: 2005-2008.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">v3: 2006-2008 -- 2008 LinuxBIOS Renamed "coreboot" -- v4: 2009-2012 -- v4+: 2012-2014 -- Further Reading -- Prerequisites for Working with coreboot -- Community Organization -- Git and Gerrit -- Git Commit Messages -- coreboot Sign-off Procedure -- Developer's Certificate of Origin 1.1 -- Adding Your Sign-off -- Working with the coreboot Community -- coreboot Do's -- coreboot Don'ts -- Nonsource Binaries in coreboot -- A Hands-on Example: Building coreboot for the MinnowBoard MAX Mainboard -- Environment -- Hardware: MinnowBoard MAX -- MinnowBoard MAX Platform Details -- Development Directory -- Downloading Intel FSP -- Installing Intel FSP -- Downloading the coreboot Source -- coreboot Toolchain -- coreboot Commit Hooks -- Creating a coreboot Development Branch -- Building the Mainboard -- On the Menuconfig Menu -- On the Chipset Menu -- On the Devices Menu -- Build -- Summary of Commands -- Flashing the ROM -- Preparing the Flash Programmer -- Flashing the ROM Image -- coreboot Internals -- Boot Stages -- Additional Files -- CBFS -- An Example of CBFS -- CBFS Size -- Special Binaries -- Boot Flow Using Intel FSP -- Reset Vector and Bootblock -- romstage -- ramstage -- Payload -- coreboot Source -- coreboot Device Tree -- Chips and Devices -- Device Tree Variables -- A Device Tree Example -- Chip Operations -- Device Operations -- coreboot Hardwaremain State Machine -- State Machine States -- State Machine Callbacks -- Mainboard -- The Chipset Driver -- Chipset FSP UPD Options -- The FSP Driver -- Kconfig -- xcompile -- Payloads -- SeaBIOS -- GRUB 2 -- FILO -- iPXE -- TianoCore -- Depthcharge -- U- Boot -- Memtest86+ -- libpayload -- coreboot Troubleshooting and Debugging -- Postcodes -- Serial Debug -- EHCI USB Debug -- Summary -- Chapter 5: Chrome book Firmware Internals -- About Chrome book and Chrome OS -- Chrome OS Firmware Overview.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Chrome OS Security Philosophy -- Chrome OS Security Guiding Principles -- Power wash -- Chrome OS Boot Modes -- Verified (Normal) Mode -- Recovery Mode -- Developer Mode -- Chrome OS Coreboot -- x86 -- ARM -- Depth charge Payload -- libpayload -- Verified Boot -- Verified Boot and Kernel Security -- Chrome OS Firmware Boot Log -- Boot Times Log -- Chrome OS Firmware Event Log -- Google SMI Linux Kernel Driver -- Chrome OS Extensions to the Firmware Image -- FMAP -- BOOT_STUB FMAP Section -- Chrome OS Firmware RW FMAP Sections -- An fmap.dts (RW_SECTION_A) Example -- Google Binary Block (GBB) -- GBB: HWID v3 -- GBB: Firmware Bitmaps -- GBB: Firmware Keys -- GBB: Boot Flags -- Vital Product Data ( VPD) -- Firmware TPM Usage -- Chrome OS Firmware Update -- Chrome OS Utilities -- flashrom -- gbb_utility -- GBB Flags Utility Script: set_gbb_flags.sh -- crossystem -- mosys -- Google Embedded Controller -- Power Sequencing -- Battery Charging -- Thermal Management -- Keyboard Controller -- Other Peripheral Controls -- Chrome EC Software Sync -- Software Sync Steps -- Summary -- Chapter 6: Intel FSP and UEFI Integration -- Introduction to EFI -- Introduction to FSP -- Introduction to EDK II -- Summary -- FSP Components -- FSP Wrapper Boot Flow -- Generic FSP Wrapper Boot Flow -- Normal Boot -- Boot Flow -- Memory Layout for a Normal Boot Flow -- FSP Normal Boot Data Structure -- S3 Boot -- Boot Flow -- S3 Memory Layout -- S3 NV Data Passing -- Capsule Flash Update -- Boot Flow -- Capsule Update Memory Layout -- Recovery Boot Flow -- FSP Recovery Memory Layout -- coreboot Payload Based upon EDK II -- Building Minnow and MinnowMax with FSP -- Future of the Intel FSP -- Conclusion -- Chapter 7: Building Firmware for Quark Processors -- Overview of UEFI and PI -- History of Implementations and Specifications -- Introduction to EDK II Building Blocks.</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">PKG: Packaging -- MdePkg -- MdeModulePkg -- IntelFrameworkPkg -- IntelFrameworkModulePkg -- Packages -- PCD: Platform Configuration Database -- Syntax -- DEC: Platform Declaration File -- Syntax -- DSC: Platform Description File -- FDF: Flash Description File -- Syntax -- Build: The EDK II Build Command -- INF: INF File -- More Information -- Introduction to the EDK II Subset -- Introduction to Quark -- ROM Flash Image Size Optimization -- Fixed Resource -- DRAM/SMRAM -- Remove Features -- Reduce Features -- Compiler Options -- Build Options -- Results of the TinyQuark Optimization -- RAM Footprint Optimization -- Optimization -- Result of Memory Usage Optimization -- Conclusion -- Chapter 8: Putting It All Together -- RTOS and Intel FSP -- Intel FSP and Open Source Philosophy -- Customization and Production of Intel FSP -- It Is a Community Effort After All -- Appendix A: Sample Boot Setting File (BSF) -- Index.</subfield></datafield><datafield tag="588" ind1=" " ind2=" "><subfield code="a">Description based on publisher supplied metadata and other sources.</subfield></datafield><datafield tag="590" ind1=" " ind2=" "><subfield code="a">Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2024. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries. </subfield></datafield><datafield tag="655" ind1=" " ind2="4"><subfield code="a">Electronic books.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sun, Jiming.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Jones, Marc.</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Reinauer, Stefan.</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Print version:</subfield><subfield code="a">Zimmer, Vincent</subfield><subfield code="t">Embedded Firmware Solutions</subfield><subfield code="d">Berkeley, CA : Apress L. P.,c2015</subfield><subfield code="z">9781484200711</subfield></datafield><datafield tag="797" ind1="2" ind2=" "><subfield code="a">ProQuest (Firm)</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://ebookcentral.proquest.com/lib/oeawat/detail.action?docID=6422674</subfield><subfield code="z">Click to View</subfield></datafield></record></collection> |